The present invention relates to methods of forming integrated circuit devices and device formed thereby and, more particularly, to methods of forming integrated circuit devices having nano-scale features therein and integrated circuit devices formed thereby.
As semiconductor devices scale down to nano-scale dimensions (i.e., xe2x89xa6100 nm features), the performance improvements predicted by Moore""s Law typically diminish. Some fundamental physical properties, such as direct quantum tunneling through gate dielectrics, poly depletion in gate electrodes and source-drain leakage due to short channel effects, may become limiting factors in performance and may inhibit further scaling of conventional devices.
One method to suppress short channel effects in field effect transistors is to make the semiconductor channel of the transistor sufficiently thin that it becomes fully depleted during operation. One such device is a planar thin-body semiconductor-on-insulator (SOI) transistor, where the source-drain leakage current can be controlled by a high quality back oxide. However, the thin-body SOI transistor may suffer from poor drain-induced barrier lowering and significant short channel threshold voltage reduction due to reach-through of the drain field through a bulk oxide region. The dual-gate MOSFET with both a front gate and a back gate can provide an effective solution to the problems encountered by thin-body SOI transistors. An extension of the dual-gate transistor is the surround gate transistor, which includes a gate that wraps around (i.e., surrounds) the channel.
Several double/surround gate devices that have been proposed can be classified as either horizontal devices or vertical devices. In horizontal devices, the gate length can be defined using photolithography techniques. However, conventional photolithography techniques may not efficiently scale to nano-scale dimensions. In vertical devices, conventional photolithography techniques may not be required to achieve nano-scale dimensions. For example, in vertical field effect transistors, the gate length and other features may be defined by film thickness instead of a photolithographically defined line width. Conventional vertical devices, such as surround gate transistors, are disclosed in an article by E. Leobandung et al. entitled xe2x80x9cWire-Channel and Wrap-Around-Gate Metal-Oxide-Semiconductor Field-Effect Transistors with a Significant Reduction of Short Channel Effects,xe2x80x9d J. Vac. Sci. Technol., B 15(6), pp. 2791-2794, November/December (1997). Vertical devices are also disclosed in an article by C. Auth et al., entitled xe2x80x9cScaling Theory for Cylindrical, Fully-Depleted, Surrounding-Gate MOSFET""s,xe2x80x9d IEEE Elec. Dev. Lett., Vol. 18, No. 2, pp. 74-76, February (1997).
Additional devices that utilize nano-scale metal or semiconductor materials may be formed using nanowires. When wires fabricated from metal or semiconductor materials are provided in the nanometer size range, some of the electronic and optical properties of the metal or semiconductor materials at nano-scale dimensions may be different from the same properties of the same materials at a larger scale. Semiconductor structures in the nanometer size range that exhibit the characteristics of quantum confinement are typically referred to as zero-dimension (OD) quantum dots or more simply as quantum dots when the confinement is in three dimensions. Quantum dots may be provided by semiconductor materials having one or more dimensions on the scale of about ten nanometers or less. When quantum confinement is in two dimensions, the structures are typically referred to as one-dimensional quantum wires or more simply as quantum wires. A quantum wire is a wire having a diameter sufficiently small to cause confinement of an electron gas in directions that extend normal to the wire.
A prior art technique for fabricating quantum wires may utilize a micro-photolithographic process followed by a metalorganic chemical vapor deposition (MOCVD) process. This technique may be used to generate a single quantum wire or a row of gallium arsenide (GaAs) quantum wires embedded within a bulk aluminum arsenide (AlAs) substrate. However, such techniques may not be compatible with processes to form two or three dimensional arrays of nanowires in which the spacing between nanowires is relatively small and uniform.
Additional techniques for forming two-dimensional arrays of nano-channels include filling naturally occurring arrays of nano-channels or nanopores in a substrate with a material of interest. In this manner, the substrate is used as a template. Exemplary substrates include anodic aluminum oxide and mesoporous materials, which may be provided with arrays of pores therein. In particular, U.S. Pat. No. 6,359,288 to Ying et al. discloses techniques for forming arrays of nanowires in anodic aluminum oxide substrates. One of these techniques includes systematically changing the channel diameter and channel packing density of an anodic aluminum oxide layer by anodizing an aluminum layer with an electrolyte to provide an anodic aluminum oxide layer having nanopores therein. The mean pore diameter is disclosed as varying by no more than 100% along the length of the pore. The ""288 patent also discloses filling the pores with single crystal material so that the resulting nanowires constitute single crystal quantum wires. These quantum wires may have an average wire diameter in a range of about 1 nm to about 20 nm. U.S. Pat. No. 6,231,744 to Ying et al. also discloses a method of forming a nanowire array by anodizing an aluminum substrate using an acidic electrolyte solution to provide a porous aluminum oxide film (i.e., anodic aluminum oxide (AAO) film) on a surface of an aluminum substrate. The porous AAO film is then exposed to an acid etchant solution for a period of time sufficient to enlarge the cell size of the pores.
Techniques for forming porous films and nano-scale electronic devices are disclosed in European Patent Specification No. EP 0 178 831 B1 and in U.S. Pat. No. 6,034,468 to Wilshaw. In particular, the ""468 patent to Wilshaw discloses a field emitter device having a dielectric AAO layer therein with nanopores. The front ends of the wires constitute individual field emitting cathodes. A gate electrode is also provided on a front surface of the AAO layer. U.S. Pat. No. 5,581,091 to Moskovits et al. also discloses single-electron devices that are useful as diodes and transistors. These devices are prepared by anodizing a metal substrate in an acid bath to convert the metal substrate into an oxide film.
Embodiments of the present invention include nano-scale electronic devices and methods of forming nano-scale electronic devices using techniques that advantageously have a reduced number of photolithographically defined processing steps. Some of these electronic devices constitute field effect transistors having surround gates that provide fully depleted operation. Other embodiments include opto-electronic devices that contain compound semiconductor materials.
Methods according to embodiments of the present invention include forming a vertical nano-scale electronic device by forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. The substrate insulating layer may contact an upper surface of the semiconductor layer. A step is then performed to form an etching template having a first array of non-photolithographically defined nano-channels extending therethrough, on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.
The step of forming an etching template may include forming a metal film (e.g., aluminum film) on the substrate insulating layer and then repeatedly anodizing the metal film to convert it into an anodic metal oxide layer having nano-channels therein. The selective etching step may also include ion etching or reactive ion beam etching the insulating layer for a sufficient duration to penetrate the substrate insulating layer and expose the semiconductor layer. The semiconductor layer may also constitute a monocrystalline semiconductor layer and the step of forming an array of semiconductor nano-pillars may include epitaxially growing monocrystalline semiconductor nano-pillars using the monocrystalline semiconductor layer as a seed layer.
These methods may also include the steps of removing the substrate insulating layer to expose the semiconductor nano-pillars and then implanting dopants of first conductivity type into upper surfaces of the semiconductor nano-pillars to define respective drain regions therein. Gate insulating layers are then formed on sidewalls of the semiconductor nano-pillars. A global surround gate electrode may then be formed that extends on the gate insulating layers and in recesses between the semiconductor nano-pillars. A drain electrode may be formed that contacts the drain regions in the semiconductor nano-pillars.
The step of forming a drain electrode may be preceded by the step of depositing an electrically insulating passivation layer on the surround gate electrode and etching-back the passivation layer to expose the upper surfaces of the semiconducting nano-pillars. The step of implanting dopants may also be preceded by the steps of forming a sacrificial protective layer on upper surfaces and sidewalls of the semiconductor nano-pillars and then etching-back the sacrificial protective layer to expose the upper surfaces of the semiconducting nano-pillars. The sacrificial protective layer may then be removed entirely before the gate insulating layer is formed on sidewalls of the semiconducting nano-pillars.
Additional methods of forming vertical nano-scale electronic devices may include forming a substrate comprising a semiconductor layer, a substrate insulating layer on the semiconductor layer and a barrier metal layer on the substrate insulating layer. An etching template is then formed on the substrate insulating layer. The etching template has a first array of non-photolithographically defined nano-channels or nanopores extending therethrough. The etching template may be formed by depositing a metal film (e.g., aluminum film) on the barrier metal layer and then anodizing the metal film into an anodic metal oxide layer having an array of nanopores therein. The barrier metal layer is then selectively etched so that the nanopores extend through the barrier metal layer and expose the substrate insulating layer. The anodic metal oxide layer and the barrier metal layer collectively form the etching template. The substrate insulating layer is then selectively etched for a sufficient duration to define a second array of nano-channels therein and expose the semiconductor layer. The substrate insulating layer may comprise silicon dioxide or silicon nitride, for example. Other electrically insulating materials may also be used. This etching step is performed in order to transfer the pattern of the first array of nano-channels in the etching template to the underlying substrate insulating layer. Selective growth techniques may then be used to grow an array of semiconductor nano-pillars that extend upward from the semiconductor layer and into the second array of nano-channels.
Methods of forming nano-scale opto-electronic devices are also provided by embodiments of the present invention. These methods may include forming a substrate comprising a first compound semiconductor layer of first conductivity type that is a composite of first and second III-V semiconductor materials (e.g., GaAs and AlGaAs). An electrically insulating layer (e.g., SiO2) is then formed on the first semiconductor layer. A step is performed to form a metal thin film on the electrically insulating layer. The metal thin film is converted into an anodized metal oxide layer having an array of nanopores therein. This step to convert the metal thin film into an anodized metal oxide layer is preferably performed without using a photolithographically defined mask to guide the conversion process. The array of nanopores within the anodized metal oxide layer is then transferred to the electrically insulating layer. An array of vertical quantum-dot superlattices is epitaxially grown upward from the underlying first semiconductor layer, using the array of nanopores to guide the epitaxial growth step. A second compound semiconductor layer of second conductivity type may be formed on the array of vertical quantum-dot superlattices. This second compound semiconductor layer may comprise a composite of the first and second III-V semiconductor materials, for example.
Additional embodiments of the present invention include preferred optoelectronic devices that contain arrays of vertical quantum-dot superlattices therein. An optoelectronic device may include a substrate having a first III-V semiconductor layer therein. An electrically insulating layer is also provided that extends on the first III-V semiconductor layer. This electrically insulating layer includes an array of non-photolithographically defined nanopores therein. An array of vertical quantum-dot superlattices are provided in the array of nanopores. These vertical quantum-dot superlattices are electrically coupled to the first III-V semiconductor layer. The optoelectronic device may also include a second III-V semiconductor layer that extends on the array of vertical quantum-dot superlattices. According to a preferred aspect of this embodiment, the first and second III-V semiconductor layers are homoepitaxial or heteroepitaxial with the vertical quantum-dot superlattices.